1. Field of the Invention
The present invention relates to a burst light receiving power monitor circuit that measures the light receiving power of burst cells. In particular, the present invention relates to a burst light receiving power monitor, method, and program capable of monitoring the light receiving power of all burst cells as needed.
2. Description of the Related Art
FIG. 1 is a block diagram of a schematic configuration of an optical module as a basis of the present invention. In the present description and the drawings, the same constituent elements are designated with the same reference numerals and symbols throughout the drawings. As shown in FIG. 1, optical module 100 comprises PD (photodiode) 101, TIA (transimpedance amplifier) 102, LIM (limiting amplifier) 103, current mirror circuit 104, current/voltage converter circuit 105, ADC (analog/digital converter) 106, and control circuit 107 and includes a reception function.
PD 101 converts received light to an electric current.
TIA 102 is connected to the anode side of PD 101 and is a transimpedance amplifier which correspond to burst signal, and converts a current signal to a voltage signal. TIA 102 modulates the light received in PD 101 to an electrical signal.
LIM 103 is connected to TIA 102 and amplifies an input signal level, which varies according to the reception state, to an output signal of a certain level to form a main output signal.
Current mirror circuit 104 is connected to the cathode side of PD 101 and is a constant current source circuit. Current mirror circuit 104 outputs the same current as input current.
Current/voltage converter circuit 105 is connected to current mirror circuit 104 and converts an input current to a voltage before outputting.
ADC 106 is connected to current/voltage converter circuit 105 and converts an inputted voltage from analog to digital.
Control circuit 107 is connected to ADC 106, imports a digital voltage signal from current/voltage converter circuit 105, and imports a control signal as a trigger from outside according to the timing of a burst cell.
Memory 108 is arranged in control circuit 107, and the digital voltage signal from current/voltage converter circuit 105 is imported and stored in area 109 of memory 108 in burst cells. The digital voltage signal stored in memory 108 is read out by an external memory access signal from a memory access input/output terminal and is used to monitor the light receiving power of burst cells.
FIG. 2 is an explanatory view of an operation example of monitoring the light receiving power of burst cells of optical module 100 in FIG. 1. As shown in FIG. 2(A), optical module 100 processes input signal light for burst cells 200-1, 200-2, 200-3, . . . , and 200-N that are burst-transmitted. As shown in FIG. 2(B), control circuit 107 imports monitor voltage digital amplitudes P1, P2, P3, . . . , and PN relative to the input signal light of burst cells 200-1, 200-2, 200-3, . . . , and 200-N.
As shown in FIG. 2(C), a control signal is inputted to control circuit 107.
As shown in FIG. 2(D), monitor voltages p1, p2, p3, . . . , PN are sequentially stored in area 109 of memory 108 with the control signal serving as a trigger.
FIG. 3 is a flow chart for explaining an example of a series of operations of control circuit 107 of optical module 100 in FIG. 1. As shown in FIG. 3, k=1 is set in control circuit 107 in step S301.
In step S302, control circuit 107 imports monitor voltage Pk.
In step S303, control circuit 107 stores inputted monitor voltage Pk in memory 108.
In step S304, control circuit 107 uses a memory access signal to check whether there is a request to read out monitor voltage Pk. If it cannot be confirmed, the process proceeds to step S306.
In step S305, if there is a request to read out monitor voltage Pk, control circuit 107 reads out monitor voltage Pk from memory 108.
In step S306, control circuit 107 deletes monitor voltage Pk that is stored in memory 108. The deletion is for the preparation of the next storage. Rather than being deleted, monitor voltage Pk may be stored immediately before the process of step S303, and the next monitor voltage Pk+1 may overwrite monitor voltage Pk in step S303.
In step S307, whether k=N is checked. If this cannot be confirmed, the process proceeds to step S309.
In step S308, k=k+1 is executed. The process then returns to step S302, and the above processes are repeated.
In step S309, the process proceeds to step S301 if there is no request for reception termination, and the above processes are repeated to allow monitoring of all burst light continuously received in the actual operation. If there is a request for reception termination, the process ends.
As described, there is only one area 109 in memory 108 for storing monitor voltages as light receiving power. Therefore, there is a problem in that only one part of burst cells can be monitored at once.
Thus, as shown in FIG. 2, only one monitor voltage can be read out for each control signal input.
This is because a procedure that executes a conversion process of ADC 106 by using a control signal, inputting to control signal to control circuit 107, storing it memory 108 and reading out a stored value from memory 108 is required to monitor the light receiving power of burst cells.
For example, all data of burst cells 200-1, 200-2, 200-3, . . . , 200-N cannot be read out at once, and the procedure needs to be repeated for N times, thus the procedure cannot provide an immediate result. Furthermore, the monitor voltage of one required arbitrary burst cell cannot be read out immediately, thus the procedure cannot provide an immediate result.
There is also a problem that it is impossible to set the alarm for the monitor voltage of a burst cell that is not power-monitored.
Examples of techniques related to such an optical module include the following.
A technique described in Japanese Patent Laid-Open No. 2002-057627 provides a system and a method for improving transmission efficiency with a relatively simple configuration. In an optical communication system including substations connected to a master station through an optical coupler, the master station comprises: a light level detector that measures a reception level of an optical signal transmitted from each substation to the master station to generate measurement information; a storage unit that stores the measurement information for each substation generated in the light level detector in association with the substation; a controller that generates adjustment information to make an optical signal level constant at the maximum level based on the measurement information of substations read out from the storage unit; an optical amplifier that amplifies the optical signal level from the substations based on adjustment information from the controller; a light receiver that converts an output of the optical amplifier to an electrical signal; and a received data processor that receives the signal outputted from the light receiver as a received signal.
The technique described in Japanese Patent Laid-Open No. 2002-057627 makes the optical signal level constant at the maximum level based on the measurement information of the substations read out from the storage unit that stores the measurement information for each substation generated by the light level detector in association with the substation. However, the technique does not solve the problem in which the monitor voltage of a required arbitrary burst cell cannot be immediately read out, thus this technique cannot provide an immediate result.
A technique described in Japanese Patent Laid-Open No. 10-243041 can obtain a stable frame signal with a fast reaction to the input even if the input level is low, can prevent a reduction in transmission efficiency, and can prevent narrowing down of the dynamic range of the input level. In the technique described in Japanese Patent Laid-Open No. 10-243041, a logarithmic amplifier outputs a power level of a modulated wave input as a logarithmic value, and an integrator smoothes the logarithmic value and outputs RSSI. A comparator compares properly set reference value REF and RSSI and outputs a ‘LO’ frame signal if RSSI is lower, i.e. in a section with no signal. The comparator outputs a ‘HI’ frame signal if RSSI is higher, i.e. in a section with a signal. A timer circuit is fixed to ‘HI’ unless the comparator output is continuously ‘LO’ for more than one clock cycle. After the comparator output is fixed to “LO”, if two clocks CLK are inputted, the timer circuit output becomes ‘HI’, and the timer output is fixed to ‘HI’ until the comparator output again becomes ‘HI’.
In the technique described in Japanese Patent Laid-Open No. 10-243041, the comparator compares properly set reference value REF and RSSI, the reaction to an input is fast, a stable frame signal can be obtained even if the input level is low, transmission efficiency is not reduced, and the dynamic range of the input level is not narrowed down. However, the technique does not solve the problem that the monitor voltage of a required arbitrary burst cell cannot be immediately read out, thus this technique cannot provide an immediate result.